document number: 85182 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 01-jul-10 1 two-line esd-protection in sot-23 gsot05cl-v vishay semiconductors marking (example only) yyy = type code (see table below) xx = date code features ? two-line esd-protection device ? esd-protection acc. iec 61000-4-2 30 kv contact discharge 30 kv air discharge ? space saving sot-23 package ? aec-q101 qualified ?e3 - sn ? compliant to rohs directive 2002/95/ec and in accordance to weee 2002/96/ec 20512 1 20456 2 3 1 20357 yyy xx xx ordering information device name environmental status ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity gsot05cl-v standard gsot05cl-v-gs08 3000 15 000 green GSOT05CL-V-G-08 package data device name package name type code environmental status weight molding compound flammability rating moisture sensitivity level soldering conditions gsot05cl-v sot-23 5cl standard 8.8 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals clg green 8.1 mg absolute maximum ratings gsot05cl-v parameter test conditions symbol value unit peak pulse current pin 1 to 3 or pin 2 to 3 acc. iec 61000-4-5, t p = 8/20 s; single shot i ppm 13 a pin 1 to 2 or pin 2 to 1; pin 3 not connected acc. iec 61000-4-5, t p = 8/20 s; single shot 13 a peak pulse power pin 1 to 3 or pin 2 to 3 acc. iec 61000-4-5, t p = 8/20 s; single shot p pp 156 w pin 1 to 2 or pin 2 to 1; pin 3 not connected acc. iec 61000-4-5, t p = 8/20 s; single shot 156 w esd immunity contact discharge acc. iec 61000-4-2; 10 pulses v esd 30 kv air discharge acc. iec 61000-4-2; 10 pulses 30 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t stg - 55 to + 150 c ** please see document vishay material category policy: www.vishay.com/doc?99902
www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 85182 2 rev. 1.2, 01-jul-10 gsot05cl-v vishay semiconductors two-line esd-protection in sot-23 bias-mode (2-line bidirectional asymme trical protection mode) with the gsot05cl-v two signal- or data-lines (l1, l2) can be protected against voltage transients. with pin 3 connected to ground and pin 1 and pin 2 connected to a signal- or data-line which has to be protected. as long as the voltage level on the data- or signal-line is between 0 v (ground level) and the specified maximum reverse working voltage (v rwm ) the protection diode between pin 2 and pin 3 and between pin 1 and pin 3 offe r a high isolation to the ground line. the protection device behaves like an open switch. as soon as any positive transient voltage signal exceeds the break through voltage level of th e protection diode, the diode becomes conductive and shorts the transien t current to ground. now the protection de vice behaves like a closed switch. the clamping voltage (v c ) is defined by the br eakthrough voltage (v br ) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. any negative transient signal w ill be clamped accordingly. the negative transien t current is flowing in the forward direction o f the protection diode. the low forward voltage (v f ) clamps the negative transient close to the ground level. due to the different clamping levels in forward and reverse direction the gsot05cl-v clamping behaviour is bidirectional and asymmetrical (bias). if a higher surge current or peak pulse current (i pp ) is needed, both protection diodes in the gsotxxc can also be used in parallel in order to dou ble the performance. this offers: ? double surge power = double peak pulse current (2 x i ppm ) ? half of the line inductance = reduced clamping voltage ? half of the line resistance = reduced clamping voltage ? double line capacitance (2 x c d ) ? double reverse leakage current (2 x i r ) note ? bias mode (between pin 1 to pin 3 or pin 2 to 1) l1 l2 20358 2 1 3 g round bias l 2035 2 3 g round electrical characteristics gsot05clv parameter test conditions/remarks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel --1lines reverse working voltage at i r = 1 a v rwm 5.5 6.1 7 v reverse current at v r = 5.5 v i r --1a reverse breakdown voltage at i r = 1 ma v br 66.75- v reverse clamping voltage at i pp = 1 a v c -6.99 v at i pp = i ppm = 13 a - 10 12 v forward clamping voltage at i pp = 1 a v f -11.3v at i pp = i ppm = 30 a - 2.6 3 v capacitance at v r = 0 v; f = 1 mhz c d - 100 120 pf at v r = 2.5v; f = 1 mhz - 60 - pf
document number: 85182 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 01-jul-10 3 gsot05cl-v two-line esd-protection in sot-23 vishay semiconductors bisy-mode (1-line bidirectional symme trical protection mode) if a bipolar symmetrical protectio n device is needed the gsot05cl-v can also be used as a single line protection device. therefore pin 1 has to be connected to th e signal- or data-line (l1) and pin 2 to ground (or vice versa). pin 3 must not be connected. positive and negative voltage transients will be clamped in the same way. the clamping cu rrent through the gsot05cl-v passes one diode in forward directio n and the other one in reverse direction. the clamping voltage (v c ) is defined by the breakthrough voltage (v br ) level of one diode plus the forward voltage of th e other diode plus the voltage drop at the series impedances (resistances and inductances) of the protection device. due to the same clamping levels in positive and negative dire ction the gsot05cl-v voltage clamping behaviour is bidirectional and symmetrical (bisy). note ? ratings at 25 c, ambient temperature unless otherwise specified. bias mode (between pin 1 to 2 or pin 2 to 1; pin 3 not conne cted) typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 w/150 pf) fig. 2 - 8 /20 s peak pulse current wave form acc. iec 61000-4-5 l1 20361 2 1 3 g round bi s y electrical characteristics gsot05cl-v parameter test conditions/re marks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel --1lines reverse working voltage at i r = 1 a v rwm 6--v reverse current at v r = 6 v i r --1a reverse breakdown voltage at i r = 1 ma v br 6.5 7.5 - v reverse clamping voltage at i pp = 1 a v c -810v at i pp = i ppm = 13 a - 12.6 15 v capacitance at v r = 0 v; f = 1 mhz c d -5060pf at v r = 2.5 v; f = 1 mhz - 37 - pf 0 % 20 % 40 % 60 % 80 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 80 90 100 time (ns) discharge c u rrent i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 010203040 time ( s) i ppm 20 s to 50 % 8 s to 100 % 20548
www.vishay.com for technical questions, contact: esdprotection@vishay.com document number: 85182 4 rev. 1.2, 01-jul-10 gsot05cl-v vishay semiconductors two-line esd-protection in sot-23 fig. 3 - typical capacitance cd vs. reverse voltage vr fig. 4 - typical forward current if vs. forward voltage vf fig. 5 - typical reverse voltage vr vs. reverse current ir fig. 6 - typical peak clamping voltage vc vs. peak pulse current ipp fig. 7 - typical peak clamping voltage vc vs. peak pulse current ipp fig. 8 - typical clamping performance at + 8 kv contact discharge (acc. iec 61000-4-2) v r ( v ) c d (pf) 21918 0 20 40 60 80 100 120 0123456 f = 1mhz pin 1 to 3 or pin 2 to 3 pin 1 to 2 or pin 2 to 1 v f ( v ) i f (ma) 21919 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 10 2 1 pin 1 to 3 or pin 2 to 3 i r ( a) v r ( v ) 21920 0 1 2 3 4 5 6 7 8 9 0.01 0.1 1 10 100 1000 10 000 pin 1 to 3 or pin 2 to 3 pin 1 to 2 or pin 2 to 1 i pp (a) v c ( v ) 21921 - 15 - 10 - 5 0 5 10 15 0246810121416 pin 1 to 3 or pin 2 to 3 meas u red acc. iec 61000-4-5 (8/20 s - w a v e form) v c positi v e s u rge negati v e s u rge i pp (a) v c ( v ) 21925 - 15 - 10 - 5 0 5 10 15 0246810121416 pin 1 to 2 meas u red acc. iec 61000-4-5 (8/20 s - w a v e form) v c positi v e s u rge negati v e s u rge t (ns) v c-esd ( v ) 21922 - 60 - 40 - 20 0 20 40 60 80 - 10 0 10 20 30 40 50 60 70 80 90 acc. iec 61000-4-2 + 8 k v contact discharge pin 1 to 3 or pin 2 to 3 pos. discharge
document number: 85182 for technical questions, contact: esdprotection@vishay.com www.vishay.com rev. 1.2, 01-jul-10 5 gsot05cl-v two-line esd-protection in sot-23 vishay semiconductors fig. 9 - typical clamping performance at - 8 kv contact discharge (acc. iec 61000-4-2) fig. 10 - typical peak. clamping voltage at esd contact discharge (acc. iec 61000-4-2) package dimensions in millimeters (inches): sot-23 t (ns) v c-esd ( v ) 21923 - 80 - 60 - 40 - 20 0 20 40 60 - 10 0 10 20 30 40 50 60 70 80 90 acc. iec 61000-4-2 - 8 k v contact discharge pin 1 to 3 or pin 2 to 3 neg. discharge 21924 v c-esd ( v ) v esd (k v ) - 250 - 200 - 150 - 100 - 50 0 50 100 150 200 250 0 5 10 15 20 25 30 v c-esd acc. iec 61000-4-2 contact discharge pin 1 to 3 or pin 2 to 3 foot print recommendation: rev. 8 - date: 23. s ept.2009 17418 document no.: 6.541-5014.01-4 0.9 (0.035) 1 (0.039) 0.9 (0.035) 1 (0.039) 1.43 (0.056) 0.45 (0.018) 0.35 (0.014) 2.8 (0.110) 3.1 (0.122) 0.45 (0.018) 0.35 (0.014) 0.45 (0.018) 0.35 (0.014) 0.1 (0.004) max. 2.35 (0.093) 2.6 (0.102) 0.175 (0.007) 0.098 (0.004) 1.15 (0.045) 0.9 (0.035) 1.20 (0.047) 0.95 (0.037) 0.95 (0.037) 2 (0.079) 0.7 (0.028) 0.9 (0.035) 0 to 8 0.2 (0.008) 0.3 (0.012) 0.5 (0.020) 0.550 ref. (0.022 ref.)
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